How to build a computer

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19 Feb 2012 19:35

rurwin

…work in progress …

We left the story with the ENIAC pretending to be a stored program computer, and with the Manchester Small Experimental Machine, "Baby", just pipping it to the post.

The Von Neumann Model

The structure of a computer was described by John von Neumann in 1945 in his report on the progress in designing the successor to ENIAC, called EDVAC. Almost every computer designed since uses this same model.

We have the Central Processing Unit, where all the hard work is done, and then we connect input, output, working storage and permanent storage. The input in Neumann's time was punch cards and paper tape, the output was the same or a printer, the working storage was mercury delay line or Williams-Kilburn Tube, and the permanent storage would have been magnetic drum. (Magnetic drum is like magnetic disk, but instead of being a disk, it's a cylinder. The read/write heads are fixed in position and there are lots of them; 64 on the Manchester Mark I.)

Nowadays, the input is more likely to be a keyboard, output is the screen, working storage is the RAM (memory) and permanent storage is the hard-disk.

The Central Processing Unit

Outline of the operation of the CPU. This is not an accurate representation of any existing computer, since they are all different.

Green: Data pathways
Brown: Address pathways
Blue: Control pathways

The Central Processing Unit is further broken down in the diagram to the right. This is the sort of detail that an A-level student might have to understand. At this level of detail, every computer is different to some extent, but this will allow us to get some feel for what is going on. So this CPU contains the following parts:

Control Unit

This is a lot of oscillators and logic gates that produce control signals for the rest of the computer.

Arithmetic and Logic Unit

This is the bit that can add numbers, and subtract them, rotate them, multiply and divide them, do boolean logic operations on them… just about everything that involves changing them. In this model it is even responsible for calculating memory addresses.

Accumulator

In this computer there is a single accumulator. These days that is somewhat rare. The accumulator holds the number that the "computer is thinking of" at any moment in time. It is very quick to access and is the implicit source and destination of calculations, so it saves space and complexity in instructions too.

English	Computerese
Think of a number	Load the value in memory location "Number" into accumulator
Add 3	Add 3 to accumulator
Multiply by 4	Multiply accumulator by 4
Subtract the number you first thought of	Subtract the value in memory location "Number" from the accumulator

Program Counter

This register holds the address of the next instruction that is to be executed.

Current Instruction Register

This register holds the instruction that is currently being executed.

Memory Address Register

This is an A-level requirement, (as are the rest of them,) otherwise I would have left it out. It holds the address that is currently being accessed. So when fetching an instruction the program counter is copied here, and when accessing data the address of that data is copied here. The contents of the Memory Address Register appear on the Address Bus.

Memory Data Register

This is another one I would have left out, but it's got to be here. When an instruction or data is read, its value appears here, and when data is being written it is copied to here. The contents of the Memory Data Register are the contents of the Data Bus; when reading the Data bus is copied to the Register, when writing the Register is copied to the Data Bus.

Data Bus? Is that a Number 9 to Hype Park?

This is logically the same as the first picture, but this is how everything is connected up in the real world.

Green: Data pathways
Brown: Address pathways
Blue: Control pathways

In computer engineering, a bus is a whole set of wires going to the same places. So in an 8-bit computer the Data Bus would be eight wires labelled D₀, D₁, D₂, D₃, D₄, D₅, D₆ and D₇ The address bus might be sixteen wires, and the control bus… varies¹.

When the CPU wants to read some data from memory, it puts the address of that data on the address bus, and it does something with the control bus. The memory, or storage, or input/output that contains that data then puts it on the data bus. Writing data is just the same but the CPU puts both the address and the data on the buses and the memory, or whatever, stores what's on the data bus into the memory location.

Everything, data, instructions, input and output all goes down the three buses, only one thing can be on the buses at any one time. The buses are outside the CPU and they are made of quite long PCB tracks or pieces of wire. That makes them slow; much slower than the signals inside the CPU. This is called the Von Neumann Bottleneck, and it is a real problem that has no real solution. This is why computers have caches; the cache is a fast memory inside the CPU that remembers what is in the last few memory locations that the CPU has accessed so if they are accessed again (which is quite likely) the CPU wont have to go out to the buses to get their values. It helps, but it isn't a proper solution.

The Memory Map

The (virtual) memory map for the Raspberry Pi

Since everything — working memory, storage, input and output is accessed using the same buses, they all have to be arranged to work together. Everything has an address, from zero up to the maximum number that can be represented on the address bus. Permanent storage, input and output generally has just a few locations each. For example a keyboard might have two locations, the first might hold the last key to be pressed, and the second might hold 1 if a new key has been pressed and 0 otherwise. Working storage (memory) of course has as many addresses as items of data it can hold. For example the Raspberry Pi has 268,435,456 bytes of memory, so it needs 268,435,456 addresses. Its first address is 3,221,225,472² and its last address is 3,489,660,928. Then the first input / output device is located at address 4,060,086,272 and the others go up from there. You don't need to commit these numbers to memory, nor even the hexadecimal versions on the diagram, which would be much easier to remember.

The Fetch, Execute Cycle

Green: Data pathways
Brown: Address pathways
Blue: Control pathways

Let's look at that picture of the CPU again, because now we want to see it working. We've just hit the reset button and everything is set to zero. Lets say the bottom of the address map is RAM and location zero holds an instruction to load the accumulator with the content of memory location 42. The control unit starts up, and sends out a series of control signals with the following effects:

1. The Program Counter (which is zero) is copied to the Memory Address Register
2. A memory read operation is performed. Whatever device answers to address zero places the content of that location on the data bus and it is copied into the Memory Data Register.
3. The Memory Data Register is copied into the Current Instruction Register.
4. The Program Counter is incremented. It now holds the value 1.
5. The various bit patterns in the Current Instruction Register are detected by the logic in the control unit. The subsequent actions are performed because of those bit patterns:
6. The value 42 is copied to the Memory Address Register
7. A memory read operation is carried out. The content of memory location 42 is placed on the data bus and copied into the Memory Data Register.
8. The content of the Memory Data Register is copied into the Accumulator.
9. Everything starts again from step 1.

This is the Fetch-Execute Cycle and it is the basis of all Von Neumann computers, (which is to say the huge majority of existing computers excepting only a tiny number of experimental machines.) Steps 1-5 comprise the Fetch operation, and steps 6-8 comprise the execute operation. Steps 6-8 are simple in this example, but in the case of more complex instructions, more steps would be required.

File name	File type	Size
bus-structure.png	PNG image	9.26 kB	Info
CPUdetail.png	PNG image	41.83 kB	Info
RPiVirtualMemoryMap.png	PNG image	5.04 kB	Info
vonNeumann.png	PNG image	6.9 kB	Info

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Footnotes

1. The minimum requirement is two signals, but there are usually several more.

2. These are virtual kernel mode addresses, you don't need to know what that means, but it is not the real physical address that goes out on the address bus. This is the address you would use if you wrote a program that accessed the input/output devices.